qoriq p1012 and p1021 communications processors overview freescale qoriq communications platforms are the next-generation evolution of our leading powerquicc communications processors. built using high-performance power architecture ? cores, qoriq platforms enable a new era of networking innovation where the reliability, security and quality of service for every connection matters. qoriq p1012 and p1021 communications processors the qoriq p1 family, which includes the p1012 and p1021 communications processors, offers the value of smart integration and efficient power intelligence for a wide variety of applications in the networking, telecom, defense and industrial markets. based on 45 nm technology for low power, the p1012 and p1021 processors provide single- and dual-core options, from 533 mhzC 800 mhz, along with advanced security and a rich set of interfaces. the p1012 and p1021 processors are ideally suited for multiservice gateways, ethernet switch controllers, wireless lan access points and high- performance general-purpose control processor applications with tight thermal constraints. the p1012 and p1021 processors are pin- compatible with the qoriq p1011, p1020 and p2 platform products, offering a six-chip range of cost-effective solutions. scaling from a single core at 533 mhz (p1012) to a dual core at 1.2 ghz per core (p2020), the combined qoriq platforms deliver an impressive 4.5x aggregate frequency range. the p1012 and p1021 platforms are fully software compatible, both featuring the e500 power architecture core and peripherals, as well as being fully software compatible with the earlier powerquicc processors. this enables customers to create a product with multiple performance points from a single board design. the qoriq p1021 dual-core processor supports both symmetric and asymmetric processing, enabling customers to further optimize their design with the same applications running on each core or serialize your application using the cores for different processing tasks. the p1012 and p1021 processors have an advanced set of features for ease of use. the 256 kb l2 cache offers incremental configuration to partition the cache between the two cores or to configure it as sram or stashing memory. qoriq p1012 and p1021 block diagram 32 kb l1 i cache power architecture ? e500 core 32 kb l1 d cache 256 kb l 2 cache 32 kb l1 i cache power architecture e500 core 32 kb l1 d cache ddr2/ddr3 sdram controller not on p1012 coherency module system bus 4-ch. dma controller 4-ch. dma controller 2x pci express ? on-chip network on-chip network 4-lane serdes tdm ethernet utopia-l2 security acceleration xor duart, 2x i 2 c, timers, interrupt control, sd/mmc, spi, 2x usb 2.0/ulpi 3x gigabit ethernet enhanced local bus controller (elbc) quicc engine accelerators and memory control networking elements core complex (cpu, l2 and frontside corenet platform cache) basic peripherals and interconnect qoriq p1012 and p1021 block diagram p series qoriq communications platforms
freescale, the freescale logo, powerquicc and qoriq are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. quicc engine and corenet are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ? 2009, 2011, 2013 freescale semiconductor, inc. document number: qoriqp1021fs rev 2 for more information, please visit freescale.com/qoriq the integrated security engine supports the cryptographic algorithms commonly used in ipsec, ssl, 3gpp and other networking and wireless security protocols. the memory controller offers future proofing against memory technology migration with support for both ddr2 and ddr3. it also supports error correction codes, a baseline requirement for any high- reliability system. the p1012 and p1021 processors integrate a rich set of interfaces, including a multiprotocol serdes, gigabit ethernet, quicc engine module, pci express ? and usb. the three 10/100/1000 ethernet ports support advanced packet parsing, flow control and quality of service features, as well as ieee ? 1588 time stampingall ideal for managing the datapath traffic between the lan and wan interface. the quicc engine module provides utopia-l2, tdm and 10/100 ethernet interfaces as well as a programmable risc engine to offload protocol termination from the main cpu cores. four serdes lanes can be portioned across two pci express ports and two sgmii ports. the pci express ports can provide connectivity to ieee 802.11n radio cards for wireless support. usb or sd/mmc interfaces can be used to support local storage. multiple memory connection ports are available, including the 16-bit local bus, a usb 2.0 controller, enhanced secure digital host controller (esdhc) and serial peripheral interface (spi). target applications the p1012 and p1021 processors serve a wide variety of applications and are well suited for various combinations of data plane and control plane workloads in networking and telecom applications. with an available junction temperature range of C40 oc to +125 oc, the devices can be used in power- sensitive defense and industrial applications, and outdoor environments less protected from the environment. the devices primarily target applications such as networking and telecom linecards. a multiservice router or business gateway requires a combination of high performance and a rich set of peripherals to support the datapath throughputs and required system functionality. the p1012 and p1021 devices offer a scalable platform to develop a range of products that can support the same feature set. the quicc engine module, as well as integrated 10/100/1000 ethernet controllers with classification and qos capabilities, are ideal for managing the datapath traffic between the lan and wan interface. pci express ports can provide connectivity to ieee 802.11n radio cards for wireless support, tdm for legacy phone interfaces to support voice and the usb or sd/mmc interfaces can be used to support local storage. the integrated security engine can provide encrypted secure communications for remote users with vpn support. technical specifications ? single (p1012) and dual (p1021) high- performance power architecture e500 cores 36-bit physical addressing double-precision floating-point support 32 kb l1 instruction cache and 32 kb l1 data cache for each core 533 mhzC800 mhz core clock frequency ? 256 kb l2 cache with ecc, also configurable as sram and stashing memory ? three 10/100/1000 mb/s enhanced three- speed ethernet controllers (etsecs) tcp/ip acceleration and classification capabilities ieee 1588 support lossless flow control rgmii, sgmii ? high-speed interfaces (not all available simultaneously) four serdes to 3.125 ghz multiplexed across controllers two pci express controllers two sgmii interfaces ? quicc engine module utopia-l2 up to two 10/100 ethernet interfaces up to four t1/e1/j1/e3 or ds-3 serial interfaces up to four hdlc interfaces with 128 channels of hdlc up to four bisync interfaces up to four uart interfaces spi interfaces gpio ? two high-speed usb controllers (usb 2.0) host and device support enhanced host controller interface (ehci) ulpi interface to phy ? enhanced secure digital host controller ? serial peripheral interface ? integrated security engine (sec 3.3) crypto algorithm support includes 3des, aes, rsa/ecc, md5/ sha, arc4, snow 3g and fips deterministic rng single pass encryption/message authentication for common security protocols (e.g., ipsec, ssl, srtp, wimax) xor acceleration ? 32-bit ddr2/ddr3 sdram memory controller with ecc support ? programmable interrupt controller (pic) compliant with openpic standard ? four-channel dma controller ? two i 2 c controllers, duart, timers ? enhanced local bus controller (elbc) ? 16 general-purpose i/o signals ? package: 689-pin wirebond power-bga (tepbga2) qoriq p1021 features qoriq platform device cores top core frequency l2 size ddr 2/3 support ge ports quicc engine serdes pci express serial rapidio tdm p1 p1011 1 800 mhz 256 kb 32-bit with ecc 3 n/a 4 2 n/a yes p1 p1020 2 800 mhz 256 kb 32-bit with ecc 3 n/a 4 2 n/a yes p1 p1012 1 800 mhz 256 kb 32-bit with ecc 3 yes 4 2 n/a in quicc engine p1 p1021 2 800 mhz 256 kb 32-bit with ecc 3 yes 4 2 n/a in quicc engine p2 p2010 1 1200 mhz 512 kb 64-bit with ecc 3 n/a 4 3 2 n/a p2 p2020 2 1200 mhz 512 kb 64-bit with ecc 3 n/a 4 3 2 n/a
|
